Low Power Digital Lock Detector Using Gating D Flip Flop

Abstract

This paper talks about the optimization of a digital lock detector for dual loop PLL. The dual loop consists of fine tuning and coarse tuning. In a conventional digital lock detector, D flip flops are used. In this paper we have replaced these D flip flops with the gate clocked D flip flops. The digital lock detector is mainly used to detect frequency variations during the operation of a digital filter of the given detector. The digital lock detector is used between these PLL’s for obtaining the frequency lock information to another PLL loop. Here we were able to decrease the output dynamic power by 12.31 mW, which is quite considerable.