Design and ASIC Implementation of Efficient 8-bit Integer Division Algorithms

Abstract

Many algorithms are developed for implementing division in hardware. This paper describes the efficient 8-bit integer division algorithms. The 8-bit division algorithms are intended and enforced Verilog code in activity model. Then the division algorithms are synthesized and enforced on ASIC Implementation. A division could be purposefully a slice of the arithmetic and logic unit and division is the one foremost difficult operation among all the fundamental arithmetic operations. In this paper we have designed 8-bit division algorithm for signed and unsigned numbers that performs specific division operations. When the results are analyzed, comparison of performance parameters (like speed, area, delay and power consumption) are optimized. Verilog Hardware Description Language (HDL) is used to verify the functionality of the considered algorithms and synthesized using cadence tool and the layout has beengenerated. Nc-launchhasbeenusedforsimulation,genus for the synthesized design and innovus is used for physical design. Compared to all proposed algorithms the restoring unsigned division algorithm consumes the total power of 0.8107 mW and minimum netlist of213.