A Fault Tolerant Pipelined Double Precision Reversible Floating Point Adder/Subtract or in FPGA

Abstract

In real world computation, the reare two methodologies by which numbers can be stored they are fixed point notation and floating point notation. Floatingpoint operations are used to a greater extent in most of the computational devices. Frequently used operation is Floating point addition and Subtraction. In Applications such as, Digital Signal Processing and Optical computingSpeed of operation and low power consumptions are the major criteria. Reversible logic provides a solution for this problem. In this paper a Double precision Pipelined Reversible floating point adder/subtractor (RFPA) is designed using KMD gates. The RFPA has Reversible Conditional swapping, Reversible adder, Reversible Normalization and Reversible round off blocks in it. The Designed RFPA is coded using Verilog and the same has been simulated using Modelsim 10.7c. Parameters such as Maximum operation frequency and logic cellutilization are calculated using Quartus Primeedition 20.2 using 10CX220YF672I5G device with respect to Cyclone 10 GX family. The results has been compared between Single precision and Double precision RFPA which shows that Double precision RFPA has greater operating speed by afactor of 1.1 at the expense of higher logic cellutilization.