High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder

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magesh.V, ashwanth .P, saicharan.S, sakthi.M, vishnu Prasad.R


Addition is one of the basic functions of mathematics. It is widely used in many VLSI applications such as the construction of specific DSP applications and microprocessors. Additionally, this adds two binary numbers, it is the core of many mathematical functions such as subtraction, multiplication, division, address counting, etc. The purpose of this project is to propose a modification of a new gateway level, to design three operand adderSum based on acquisition of the additive used to design three operator-carrying adders. Therefore, a new and faster localized construction is proposed using a number-based prediction to make a triple binary adder that consumes very little space, low power and significantly reduces adder delay in O (log2 n).

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vishnu Prasad.R, magesh.V, ashwanth .P, saicharan.S, sakthi.M, . (2021). High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder. Annals of the Romanian Society for Cell Biology, 25(6), 1984–1989. Retrieved from https://www.annalsofrscb.ro/index.php/journal/article/view/5739