A High-Performance Power Efficient Hybrid 2-4 Decoder Design

Abstract

This paper suggests a mixed logic architecture approach for implementing Low-Power, High-Performance Line Decoders. Most of the logic gates which are designed in ICs (Integrated Circuits) are by using CMOS circuits. These circuits are made up of blocks one is an nMOS pulldown block and the other is the pMOS pullup block and provide the best performance against device variations, area, and noise. The name Mixed Logic design (MLD) method combines the Pseudo-NMOS Logic with Dual Value Logic (DVL) for NAND/NOR Gates from Pass Transistor Logic (PTL), Transmission Gate Logic (TGL) for NAND/NOR Gates and CMOS logic, for implementing the Low Power (LP), reduced delay and High Performance (HP) decoders. Two additional topologies are added to the 2:4 decoders:  14-transistor Low-Power Topology intended to reduce power dissipation and a 15-transistor High Performance (HP) topology designed to reduce latency and energy dissipation while increasing performance by lowering the sum of transistors. With the above two topologies this paper also deals with a third design which involves the Pseudo nMOS Logic for designing a 2:4 Decoder with better performance than the above topologies. This design also supplies full swing capability. The logic design for 4:16 Decoder becomes easier by cutting the CMOS post decoder by using a 2:4 Decoder. This design method works for the Decoders both for with and without the Enable pin. Based on the results, we can draw a conclusion that the decoders implemented using Mixed Logic Methodology are ahead when compared to CMOS Logic design in all the constraints like power, delay, area, and performance with reduced transistor count.