Implementation of Arithmetic Logic Subsystem in a Sliced Processo r

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K.Rajeshwaran, K.Sudhakar, A.Kavitha, M.Geethalakshmi, C.Palaniappan


The designed estimated CLA (carry look-ahead adder) is swift and power (RAP-CLA). This adder will move between preliminary and precise modes of operation, making it appropriate for both error-tolerant and exact implementations. The framework, which is more space and power effective than current transportable estimated ripple carry adder, is accomplished by certain modifications. The findings show that, in the estimated mode of operation, the conceptual 32-bit adder achieves greater delay and energy reduction than the identical CLA, while maintaining a low error rate. It also has a smaller value and energy consumption than the other estimated adders investigated in this paper. Eventually, the suggested adder's usefulness is shown in two computer vision applications: smoothing and polishing. The CLA is then incorporated into the ALU, and the entire module is then used to create a module. Finally, these components are incorporated into a sliced processor to minimize area, energy, and delay.

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How to Cite
C.Palaniappan, K. K. A. M. . (2021). Implementation of Arithmetic Logic Subsystem in a Sliced Processo r. Annals of the Romanian Society for Cell Biology, 25(6), 722–729. Retrieved from