Implementation of 16-Bit Vedic Multiplier in Alu Using Verilog

Abstract

The main focus of our proposal is to implement a Vedic multiplier in an ALU using Vedic mathematical sutras.Majority of all the DSP and Networking applications are computation intensive and energy demanding, improvements in such vital aspects could result in a marvelous upgrade to the overall performance and efficiency of existing systems. They require bothaccuracy along with high performance. Conventional multipliers were based out of direct approach designs, they provide the required functionality but are not much efficient.Vedic mathematics offers many sutras or techniques to simplify design and improve efficiency. Among many such sutras, the Urdhava Triyagbhyam sutra is employed in our design to realize a 16*16 bit Vedic multiplier to be integrated with an ALU.The key to our success is that the proposed  multiplier is more power-area efficient and has reduced delay in its overall performance. The basic functionality of the project is multiplicationand the specifications are 16 bit width ALU consisting of  two 16 bit  inputs with a 32 bit output for multiplication, 16 bit output for other operations. The Vedic ALU is developed and analyzed in Cadence Digital systems using System verilog coding language along with ALDEC-Active HDL software for functional verifications.