Power Efficient VLSI Architecture of 4X4 Modified Column Bypassing Multiplier

Abstract

In this work, 4X4 multiplier which has high speed and less power dissipation is mooted using CMOS VLSI circuits. The crucial parameters in chip design are area, time, power and  speed. In the recent scenario, speed and power has made an important concept in Signal Processing practical applications. Various methods are available to optimize .The technique that has been discussed is a high-speed and Low power Multiplier designed based on our Column bypassing technique which is modified and primarily used for reducing the power activity in terms of switching. As this method offers more dynamic power savings, in spite of their interconnections.  This  paper presents a  power efficient VLSI Architecture of 4x4 multiplier. The proposed design is done CMOS Technology in Cadence Virtuoso environment with working  voltage  supply  of ±1.8v