Design of an 8-bit Low Power Flash ADCin 90-nm

Abstract

This paper presents the 90-nm GPDK CMOS technology library related to eight-bit 487MSps Flash ADC style victimization. As a comparator group and decoder, this design is composed of 2 main blocks. The decoder consists of a 2:1 multiplexer mostly based on one - of - N decoder and Buffer units. As a result, active die space and also the unit of power depletion area were additionally condensed to extend in frequency. The voltage offering capacity varies from ± 1.2V for the system. The simulation results include most of the 0.24 mW power consumption. 204p sec delay, but 0.02LSB and 0.1LSB for the measured DNL and INL.